Nonvolatile semiconductor memory devices are fundamental building blocks in prior art computer system designs. The primary mechanism by which data is stored in nonvolatile memory is the memory cell. Typical prior memory technologies provide a maximum storage capacity of one bit, or two states, per cell. Semiconductor memory cells having more than two possible states are known in the prior art, and specific references are cited at the close of the Background of the Invention.
One type of prior nonvolatile semiconductor memory is the flash electrically-erasable programmable read-only memory ("flash EEPROM"). Prior art flash EEPROMs typically allow for the simultaneous reading of several flash cells. Further, typical prior flash EEPROMs have a storage capacity that is much greater than the amount of data that can be output at any one time. Accordingly, each output of a flash EEPROM is typically associated with an array of flash cells that is arranged into rows and columns, where each flash cell in an array is uniquely addressable. When a user provides an address, row and column decoding logic within the flash EEPROM selects the corresponding flash cell.
A typical prior flash memory cell is comprised of a single field effect transistor ("FET") including a select gate, a floating gate, a source, and a drain. Information is stored in the flash cell by altering the amount of charge on the floating gate, which causes the threshold voltage V.sub.t of the flash cell to be varied. The typical prior art flash memory cell is in one of two possible states, being either "programmed" or "erased" with the erased state and the programmed state each specify a range of V.sub.t voltages. The flash cell can theoretically possess a separate identifiable state for each electron that is added to the floating gate. Practically speaking, however, prior flash cells typically have only two possible states because of inconsistencies in flash cell structure, charge loss over time, thermal considerations and inaccuracies in sensing the charge on the floating gate that affect the ability to determine the data stored in the flash cell.
To distinguish between the two possible states, the states are separated by a separation range. According to one prior method, when a flash cell is read, the current conducted by the flash cell is compared to a current conducted by a reference flash cell having a threshold voltage V.sub.t set to a predetermined reference voltage that is a voltage within the separation range. A single comparator typically makes the comparison and outputs the result.
When a flash cell is selected for reading, a biasing voltage is applied to the select gate. Simultaneously, the same biasing voltage is applied to the select gate of the reference cell. If the flash cell is programmed, excess electrons are trapped on the floating gate, and the threshold voltage V.sub.t of flash cell is increased such that the selected flash cell conducts less drain current than the reference flash cell. The programmed state of the prior flash cell is typically indicated by a logic 0. If the prior flash cell is erased, little or no excess electrons are on the floating gate, and the flash cell conducts more drain-source current than the reference cell. The erased state of the prior flash cell is typically indicated by a logic 1.
When a flash cell has three or more possible states, the prior art sensing schemes and circuits similar to that described above are inadequate. First, as a general rule, there must be at least (n-1) references for n states. This can be implemented as (n-1) reference cells. Thus, for three states, there must be two references. Typical prior art sensing schemes discriminate between two states and provide only one voltage reference. Second, the use of a single comparator in typical prior sensing schemes, without more, is not adequate to retrieve data from a multi-level flash cell.
U.S. Pat. No. 4,415,992 describes a sensing scheme for sensing the state of a memory cell capable of storing n states in which (n-1) comparators and (n-1) voltage references are used in parallel to determine the state of the memory cell. Each comparator compares a corresponding one of the (n-1) voltage references to a voltage determined by the drain-source current of the memory cell. Decoding logic is required to translate the outputs of the (n-1) comparators into (log.sub.2 n) binary bits.
U.S. Pat. No. 5,163,021 describes a sensing scheme in which n comparators are sequentially used to compare the state of a memory cell capable of storing n states to a corresponding n references. Again, decoding logic is required to translate the outputs of the (n-1) comparators into (log.sub.2 n) binary bits.
Co-pending patent application Ser. No. 08/252,680, Bauer, et al., filed Jun. 2, 1994, entitled "Sensing Scheme for Flash Memory with Multilevel Cells" describes a sensing circuit for determining a state of a memory cell having n possible states, where n is greater than 2, and wherein no decoding logic is required to translate outputs of comparators into binary bits. In the case where n is 4, the sensing circuit includes a first reference corresponding to a first threshold voltage level and a first comparator coupled to the memory cell and to the first reference. The first comparator compares a threshold voltage level of the memory cell to the first reference and provides a first result of the comparison as output. The sensing circuit further includes a second reference corresponding to a second threshold voltage level and a third reference corresponding to a third voltage level. A second comparator has one of its inputs coupled to the memory cell and its second input is selectively coupled to either the second reference or the third reference. A selector circuit selects between the second and third references in response to the first result. The selector circuit couples the second reference to the second comparator if the threshold voltage level of the memory cell is less than the first threshold voltage level. The selector circuit couples the third reference to the second comparator if the threshold voltage level of the memory cell is greater than the first voltage level.
Address transition detection ("ATD") is also well known in the art and has been widely used in binary cell memory array devices such as static random access memory (SRAM) and erasable programmable read-only memory (EPROM). The purpose of address transition detection circuitry is to increase the speed with which data can be read from memory. This is accomplished by performing operations that are required for every memory read operation as soon as an address transition has been detected.
These operations include equalizing sense amplifiers and latching previous output data. The sense amplifiers are used to increase weak signals sensed from the memory cells to be read during the read operation. Equalizing the sense amplifiers causes the amplifiers to be cleared or otherwise set up so that they are ready to process the new data to be read. Latching the previous output data causes the output data to remain static until the new data from the read operation has been output from the sense amplifiers. The previous output is latched because the output of the sense amplifiers fluctuates before it finally reaches a steady value. Latching the previous output ensures that the swing does not pass down to the outputs. Latching the output also provides a power savings because, so long as the address being read does not change, the output can be provided from the latches once the address specified has been read and its contents latched. Thus, the majority of the memory array can be powered down until the next address transition is detected.
Circuitry to equalize the sense amplifiers and latch previous output is well known in the art. In fact, both operations are normally performed during a binary cell memory read operation. ATD has not been used, however, with flash memory having multi-level cells. Therefore, it is desirable to have a method and circuitry to exploit address transition detection within a multi-level cell device, and thereby, to increase read access speed and reliability when determining the state of a memory cell having more than two possible states.